1. Field of the Invention
This invention relates to a storage module having storage cells which are arranged between word lines and bit lines and which contain a storage capacitor and a cell selector transistor, and more particularly to such a storage module in which each bit line is divided into two bit line portions by the insertion of a readout amplifier, and each bit line portion has a compensation cell arranged therein which comprises a selector transistor connected to the bit line portion and a capacitor arranged between an operating voltage and the selector transistor, wherein prior to a read-out process the connection point between the capacitor and the selector transistor of the compensation cell is charged to a different operating voltage so that at the beginning of the read-out process the bit line portion is set to a middle voltage located in the middle of the potential assigned to a binary "1" and the potential assigned to a binary "0".
2. Description of the Prior Art
Storage modules in which storage cells having transistors connected between the word lines and bit lines are well known in the art. An example of such a construction is given in the publication "Electronics", Sept. 13, 1973, Pages 116-121. In these cell fields, a storage cell is, in each case, arranged at the intersections between a word line and a bit line. A storage cell can comprise, for example, a MOS transistor, hereinafter called the cell selector transistor, and a storage capacitor. Here, the control electrode of the cell selector transistor is connected to a word line, whereas one electrode of the controlled path of the cell selector transistor is connected to a bit line and the other electrode of the controlled path is connected to the storage capacitor.
FIG. 1 illustrates a construction of a known storage field of the type mentioned above in which only one bit line and several word lines have been represented. The word lines are referenced W, whereas the bit line is referenced B. A storage cell SZ is located, in each case, at the intersection points between the word lines W and the bit line B. The storage cell comprises a MOS transistor MS, the cell selector transistor, and a storage capacitor CS. The entire cell field is divided into two zones X1 and X2. This division is effected in that each bit line B is divided into two portions BL and BR, a read-out amplifier LV being connected between these two portions of the bit line. Thus, a read-out amplifier space is formed between the two cell zones X1 and X2. The read-out amplifiers can be constructed, for example, as pulsed flip-flops, as described in the above-mentioned publication.
If the storage cells SZ comprise single transistor storage cells, the read-out signals which occur during the read-out process of the storage cell are extremely small. If storage cells which are connected to a word line are selected, and thus the control inputs of the transistors MS which are connected to the word line are supplied with a signal which renders the transistors conductive, then as a result of the capacitive coupling between the word lines and the bit lines, interference signals are coupled over to the bit lines. These interference signals are superimposed upon the read-out signals in such a way as to often prevent analysis of the read-out signals. For this reason, compensation cells (dummy cells) are provided and serve to compensate the interference signals which are coupled to the bit lines as a result of the selection of a word line. A compensation cell LZ of this type is arranged on each side of the read-out amplifier LV in each bit line portion. The compensation cell, like the storage cell SZ, in each case comprises a transistor MD, hereinafter called the compensation selector transistor, and a capacitor CD.
The compensation cells serve to compensate the interferences which are coupled to the bit lines as a result of the selection of the word line. Here, one proceeds as follows. Prior to the call-up of a word line of the cell field, the capacitors CD of the compensation cells are charged by a generator G to a voltage which lies in the middle between the potential which defines a binary "0" and the potential which defines a binary "1". This voltage is referred to as the middle voltage. On the call-up of a word line, the compensation cells arranged in the other cell zone are in each case called up. If, for example, the word line W1 is operated, the compensation cells LZ located in the cell zone are likewise operated by a signal on the line WDR. As a result of the selection of the word line W1, interferences arise on the bit line portion BL and as a result of the selection of the line WDR, interferences arise on the bit line portion BR. These interferences are fed to the read-amplifier LV and can in this matter be compensated. The same holds true when the word line WN is operated, in which case the line WDL is simultaneously selected.
If, in the known arrangement illustrated in FIG. 1, the compensation selector transistor is dimensioned in accordance with the cell selector transistor of the storage cell, and the compensation capacitor is dimensioned in accordance with the storage capacitor of the storage cell, the increase in capacitance on each bit line portion will be equal on the selection of a compensation cell and a storage cell. With the aid of the generator G, the capacitor of the compensation cell is connected to a voltage which corresponds to the middle voltage on the bit line portion. The disadvantage of this known arrangement resides in the fact that an additional generator G is required to produce the middle voltage on the bit line portion. This generator must be able to compensate component fluctuations, temperature fluctuations and supply voltage fluctuations. This requires a corresponding expense in the construction of the generator G.
For this reason, it has been proposed that the generator G in FIG. 1 be omitted and that the connection point between the compensation selector transistor MD and the capacitor CD of each compensation cell be connected to an operating voltage prevailing on the storage module. If, for example, the capacitors of the storage cells and of the compensation cells are connected to an operating voltage VDD, the connection point between the compensation selector transistor MD and the capacitor CD of the compensation cell can be connected to a different operating potential VSS prior to the initiation of the read-out process. By means of an appropriate selection of the capacitance of the capacitor CD, it is possible to again set up a middle voltage located between the "1" and the "0" voltages of the read-out signals on the bit line portion. If, for example, the voltage VDD corresponds approximately to the voltage which defines a binary "1" and the potential VSS corresponds approximately to the voltage which defines a binary "0", the capacitance CD of the compensation cell can be selected to be equal to half the capacitance of the storage capacitor CS. However, this proposal has the disadvantage that the increase in capacitance which occurs on the selection of a storage cell and a compensation cell on the assigned bit line portions differs, as a result of which the sensitivity of the arrangement is considerably reduced.